PicoSkyFTTM is designed for embedded processing functions within SoC by providing another layer of abstraction to tackle complexity and adequately respond to rapidly changing needs, and securing development and verification efforts. Rad hard by design, small size, low power and configurable architectural features optimised for hard, real-time processing make this type of processor core suitable for aerospace and other safety critical applications.
The PicoSkyFT™ is a high performance Fault Tolerant 8/16-bit embedded processor based on Harvard enhanced RISC pipelined architecture designed to provide a next generation solution that fits between the overloaded FPGAs and the hugely complex microprocessors. The processor provides a rich and powerful proprietary PicoSky ISA with 16-bit operation codes with single cycle execution on most instructions to provide throughput of 1 MIPS per MHz. The SEE tolerant design is achieved by several error mitigation techniques and incorporated fault detection, isolation and recovery policy to increase reliability. The core is customisable to suit various memory models.
Harvard enhanced RISC pipelined architecture
High performance 8/16 bit architecture, reaching ~ 1MIPS / MHz
High code density enabled by PicoSky ISA with 140 instructions
Error detection and correction on the fly without any time penalty on timing or performance
EDAC unit diagnostic functionality (bypass)
Parity protected supervisor and user Register files
Parity check diagnostic functionality (bypass)
Trap handlers invoked in case of detected faults
PartialTMR or FullTMR ready on register level with TMRcreator tool
Handles several fault sources - traps for fault mitigated and accomplishing FDIR policy
Fully user definable FDIR policy for each fault cause, respectively
Configurable program memory
Program memory models: Compact (8 kB), Small (64 kB), Medium (128 kB), Large (8 MB)
Configurable supervisor/boot section size
Configurable data memory
Data memory models: Normal (64kB) or Extended (16MB)
Configurable Interrupt Controller
Customisable number of interrupt vectors
Prioritised interrupt vectors
Debug and Test Facilities
Debug Support Unit (DSU)
Advance high speed DSU interface with PicoSkyLINK programmer/debugger
Hardware breakpoint available for ROM debugging
GNU GCC tool chain
GDB debugging support for complete core manipulation
PicoSkySIM™ cycle exact processor simulator
TMRcreator tool for automatic selective triplication
Versatile Peripheral Interface
Rich set of standard peripherals units (PicoLIB)
CAN 2.0A/B controller
WatchDog Timer controller
PicoSky/FT processor is technology independent IP core. The following table provides resources utilization and maximum frequency for Microsemi RT/ProASIC3-A3PE3000 FPGA family. Resources utilization for other FPGA vendors available upon request.
Resource utilization* [VersaTiles]
Performance benchmark [CoreMark/MHz]
* PicoSky configured as compact memory model with all available features, as debug support unit with hardware breakpoint support, multiplication instructions, trace buffer support, interrupt controller, sleep functionality, etc.
PicoSky processor technology is a smallest high performance processor core on market.
Its implementation foot-print beats all the market leading processor cores as shows resource utilization comparison table below. Its true resources advantage is even more apparent when processor is integrated into a SoC. Considering processor’s FT version represents highly optimized resource overhead.
CoreMark performance factor
[alternative / PicoSky-C]
[alternative / PicoSkyFT-C]
[PicoSkyFT-C / alternative]
* Resource utilization comparison is based on processors' utilization information available online for Microsemi ProASIC3/e FPGA target technology.
PicoSky delivers high processing power that beats to the draw almost all 8/16-bit processor architectures, despite of its smallest-footprint implementation.
PicoSkyFT fault tolerance to SEE is proven by the radiation testing campaigns with high energy protons (PSI-PFI) and ultra-high energy heavy ions (CERN NA-SPS-H8). The PicoSkyFT was implemented in FPGA susceptible to SEE. Nominal operation was obtained during 4 days of radiation test with highly accelerated environmental simulation. During irradiation no computational errors, processor hangs or other anomalies occurred. PicoSkyFT shows remarkable fault tolerance to the induced soft-errors. Radiation testing campaigns confirmed the processor is SEFI free and its 100% safe operation, thus ensuring outstanding operational robustness and computational integrity in high radiation environment. That makes processor ideal solution for aerospace or other safety critical applications.
PicoSkyFT is available under a commercial license, allowing it to be used in any commercial application. For inquiry please send us email to firstname.lastname@example.org.